ApTIna's AP0100CS Image Signal Processor (ISP) co-chip is designed for use with CMOS image sensors, targeting the high-performance analog closed-circuit television (CCTV) market. As TV line resolution (lines resoluTIon) is heading towards 650 TVL/PH and wide dynamic range (WDR) performance is as high as 120 dB, the trend in the high performance CCTV market is higher resolution and wider dynamic range. ApTIna's AP0100CS combines with its market-leading low-light CMOS sensor products to create CCTV camera solutions with high resolution and standard dynamic range (SDR) or wide dynamic range (WDR).
The AP0100CS integrates ApTIna's advanced image processing pipeline with stunning video and low light performance. With the advanced Local Tone Mapping (ALTM) function for wide dynamic range image rendering, high quality video can be generated even under very difficult high contrast lighting conditions. The AP0100CS integrates an NTSC/PAL encoder with advanced converter functionality to provide the high TV line resolution required to simulate the CCTV market.
characteristic:
Up to 1.2Mp (1280x960) Aptina sensor support
45 fps at 1.2Mp, 60 fps at 720p
Optimized for operation with HDR sensors.
Color and gamma correction
Auto exposure, auto white balance, 50/60 Hz auto flicker detection and avoidance
Adaptive Local Tone Mapping (ALTM)
Programmable Spatial Transform Engine (STE).
Pre-rendered Graphical Overlay
Two-wire serial programming interface (CCIS)
Interface to low-cost Flash or EEPROM through SPI bus (to configure and load patches, etc.)
High-level host command interface
Standalone operation supported
Up to 5 GPIO
Fail-safe IO
Multi-Camera synchronization support
Integrated video encoder for NTSC/PAL with overlay capability and 10-bit I-DAC
Key performance parameters:
application:
IP cam and CCTV - HD
Enables CCTV -HD w/ MP sensor
On the host side, a two-wire serial interface is used to control the operation of the AP0100CS, and image data is transferred using the analog or parallel interface between the AP0100CS and The host. The AP0100CS interface to the sensor also uses a parallel interface.
figure 1
Typical parallel configuration
Figure 2: “Typical Parallel Configuration,†on page 7 and Figure 3: “Typical HiSPi Configuration,â€
On page 8 show typical AP0100CS device connections.
All power supply rails must be decoupled from ground using capacitors as close as possible to the package.
The AP0100CS signals to the sensor and host interfaces can be at different supply voltage levels to optimize power consumption and maximize flexibility. Table 1 on page 9 provides the signal descriptions for the AP0100CS.
Figure 2: Typical Parallel Configuration
Note: 1. This typical configuration shows only one scenario out of multiple possible variations for this device.
2. Aptina recommends a 1.5kΩ resistor value for the two-wire serial interface RPULL-UP; however, greater
Values ​​may be used for slower transmission speed.
3. RESET_BAR has an internal pull-up resistor and can be left floating if not used.
4. The decoupling capacitors for the regulator input and output should have a value of 1.0uF. The capacitors
Should be ceramic and need to have X5R or X7R dielectric.
5. TRST_BAR connects to GND for normal operation.
6. Aptina recommends that 0.1μF and 1μF decoupling capacitors for each power supply are mounted as
Close as possible to the pin. Actual values ​​and numbers may vary depending on layout and design
Typical HISPI (High Speed ​​Serial Pixel Interface) configuration:
Figure 3: Typical HISPI Configuration
HiSPi and Parallel Connection
When using the HiSPi interface, the user should connect the parallel interface to VDDIO_S.When using the parallel interface, the HiSPi interface and power supply (VDD_PHY) can be left floating.
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