Altera's Cyclone V SoC FPGA family is based on a 28nm low-power (LP) process that delivers the lowest power required for 5G transceiver applications, reducing power consumption by 40% compared to previous product inspections. The device integrates ARM-based processors. Hardware Processor System (HPS) with more efficient logic synthesis, transceiver family and SoC FPGA family to reduce system power, cost and time to market, primarily for industrial, wireless and wireline communications, military equipment and car market. This article describes the main benefits and features of the Cyclone V SoC FPGA family, architecture diagrams, HPS features, and key features, block diagrams, and schematics of the Cyclone V SX SoC development board.
Altera's Cyclone® V FPGAs provide the industry's lowest system cost and power, along with performance levels that make the device family ideal for differenTIang your high-volume applicaTIons. You'll get up to 40 percent lower total power compared with the previous generaTIon, efficient Logic integration capabilities, integrated transceiver variants, and SoC FPGA variants with an ARM®-based hard processor system (HPS).
The Cyclone® V devices are designed to simultaneously accommodate the shrinking power consumption, cost, and time-to-market requirements; and the increasing bandwidth requirements for high-volume and cost-sensitive applications.
Enhanced with integrated transceivers and hard memory controllers, the Cyclone® V devices are suitable for applications in the industrial, wireless and wireline, military, and automotive markets.
Built on the 28-nm low power (LP) process technology, Altera's Cyclone V FPGAs deliver the lowest power solution for applications requiring up to 5G transceivers. Compared to previous generations, Cyclone V FPGAs offer a 40-percent power reduction, with a balance Of power reduction from all areas.
Figure 1. Cyclone V SoC FPGA Architecture
Figure 2. Cyclone V SoC block diagram
Hardware Processor System (HPS) Features:
925 MHz, dual-core ARM® CortexTM-A9 MPCoreTM processor
Each processor core includes:
32 KB of L1 instruction cache, 32 KB of L1 data cache
Single- and double-precision floating-point unit and NEONTM media engine
CoreSightTM debug and trace technology
512 KB of shared L2 cache
64 KB of scratch RAM
Multiport SDRAM controller with support for DDR2, DDR3, and LPDDR2 and optional error correction code (ECC) support
8-channel direct memory access (DMA) controller
QSPI flash controller
NAND flash controller with DMA
SD/SDIO/MMC controller with DMA
2x 10/100/1000 Ethernet media access control (MAC) with DMA
2x USB On-The-Go (OTG) controller with DMA
4x I2C controller
2x UART
2x serial peripheral interface (SPI) master peripherals, 2x SPI slave peripherals
Up to 134 general-purpose I/O (GPIO)
7x general-purpose timers
4x watchdog timers
High-Bandwidth HPS-to-FPGA Interconnect Backbone
Although the HPS and the FPGA can operate independently, they are tightly coupled via a high-bandwidth system interconnect built from high-performance ARM AMBA® AXITM bus bridges. IP bus masters in the FPGA fabric have access to HPS bus slaves via the FPGA- To-HPS interconnect. similar, HPS bus masters have access to bus slaves in the FPGA fabric via the HPS-to-FPGA bridge. Both bridges are AMBA AXI-3 compliant and support simultaneous read and write transactions. Up to six FPGA masters can Additionally the HPS SDRAM controller with the processor. Additionally, the processor can be used to configure the FPGA fabric under program control via a dedicated 32 bit configuration port.
HPS-to-FPGA: configurable 32, 64, or 128 bit AMBA AXI interface
FPGA-to-HPS: configurable 32, 64, or 128 bit AMBA AXI interface
FPGA-to-HPS SDRAM controller: up to 6 masters (command ports), 4x 64 bit read data ports and 4x 64 bit write data ports
32 bit FPGA configuration manager
Key advantages of the Cyclone V Series:
Key features of the Cyclone V Series:
Cyclone V SX SoC Development Board
The Altera® Cyclone® V SoC Development Kit offers a quick and simple approach to develop custom ARM® processor-based SoC designs accompanied by Altera's low-power, low-cost Cyclone V FPGA fabric.
Key features of the Cyclone V SX SoC development board:
Processor and FPGA prototyping and power measurement
Industrial networking protocols
Motor control applications*
Acceleration of image- and video-processing applications*
PCI Express® (PCIe®) x4 lane with ~1,000 MBps transfer rate (endpoint or rootport)
*Application-specific daughtercards, available separately, supporting a wide range of I/O and interface standards.
Figure 3. Outline drawing of the Cyclone V SX SoC development board
The Cyclone V SX SoC development board contains:
Cyclone V SX development board
Featured devices
Cyclone V SX SoC—5CSXFC6D6F31C6N (SoC)
MAX® V CPLD—5M2210ZF256C4N (system controller)
MAX II CPLD—EPM570GF100 (embedded USB-BlasterTM II cable)
FPGA configuration sources
Embedded USB-Blaster II (JTAG) cable
EPCQ flash (PFL)
Hard processor system (HPS)
FPGA memory
1 GB DDR3 SDRAM (32 bit)
FPGA I/O interfaces
2X 10/100 Megabit Ethernet PHYs (EtherCAT)
PCIe Gen1 x4 female connector
Universal high-speed mezzanine card (HSMC)—x4 transceivers, x16 TX LVDS, x16 RX LVDS
One serial digital interface (SDI) channel
Four SMAs for one transceiver channel
4X push buttons
2X switches
4X LEDs
HPS boot sources
128 MB quad serial peripheral interface (SPI) flash memory
Removable micro-SD card flash memory
FPGA
HPS memory
1 GB DDR3 SDRAM (32 bit) with error correction code (ECC)
128 MB quad SPI flash memory
Micro-SD card socket with 4 GB micro-SD card flash device
HPS I/O interfaces
1X USB 2.0 On-the-Go (OTG)
1X 10/100/1000 Megabit Ethernet (10MbE/100MbE/1000MbE)
1X CAN
1X UART (UART to USB bridge)
1X real-time clock (with battery backup)
1X two-line text LCD
1-/2-channel, 20 bit delta-sigma analog-to-digital converter (Linear Technology LTC2422)
4X push buttons
4X switches
4X LEDs
Clocking
Four-output programmable clock generator for FPGA reference clock inputs
125 MHz LVDS oscillator for FPGA reference clock input
148.5 MHz LVDS programmable voltage-controlled crystal oscillator (VCXO) for FPGA reference clock input
50 MHz single-ended oscillator for FPGA and MAX V FPGA clock input
100 MHz single-ended oscillator for MAX V FPGA configuration clock input
SMA input for HPS clock
Power
Laptop DC input 14-20 V adapter
System monitoring circuit
Power (voltage, current, wattage)
HSMC breakout board
HSMC loopback board
Mechanical
Board dimensions—8.19†x 5.22â€
Cyclone V SX FPGA Development Kit software content (downloadable from Table 2)
Design examples
Board test system (BTS)*
Golden System Reference Design with Board Update Portal web server
Complete documentation (see Table 2)
SoC Embedded Design Suite Standard Edition
ARM Development Studio 5 (DS-5TM) Altera Edition Toolkit
Hardware-to-software handoff tools
Linux run-time software for application development
SoC hardware libraries for firmware development
Application examples
Free software supported by Quartus® Prime Lite and Standard Edition software 
Figure 4. Block diagram of the Cyclone V SX SoC development board
Figure 5. Cyclone V SX SoC Development Board Circuit Diagram (1)
Figure 6. Cyclone V SX SoC Development Board Circuit Diagram (2)
Figure 7. Circuit diagram of the Cyclone V SX SoC development board (3)
Figure 8. Circuit diagram of the Cyclone V SX SoC development board (4)
Figure 9. Cyclone V SX SoC Development Board Circuit Diagram (5)
Figure 10. Circuit Diagram of the Cyclone V SX SoC Development Board (6)
Figure 11. Circuit diagram of the Cyclone V SX SoC development board (7)
Figure 12. Cyclone V SX SoC Development Board Circuit Diagram (8)
Figure 13. Circuit diagram of the Cyclone V SX SoC development board (9)
Figure 14. Cyclone V SX SoC Development Board Circuit Diagram (10)
Figure 15. Cyclone V SX SoC Development Board Circuit Diagram (11)
Figure 16. Cyclone V SX SoC Development Board Circuit Diagram (12)
Figure 17. Circuit Diagram of the Cyclone V SX SoC Development Board (13)
Figure 18. Circuit Diagram of the Cyclone V SX SoC Development Board (14)
Figure 19. Circuit Diagram of the Cyclone V SX SoC Development Board (15)
Figure 20. Cyclone V SX SoC Development Board Circuit Diagram (16)
Figure 21. Cyclone V SX SoC Development Board Circuit Diagram (17)
Figure 22. Cyclone V SX SoC Development Board Circuit Diagram (18)
Figure 23. Cyclone V SX SoC Development Board Circuit Diagram (19)
Figure 24. Cyclone V SX SoC Development Board Circuit Diagram (20)
Figure 25. Cyclone V SX SoC Development Board Circuit Diagram (21)
Figure 26. Cyclone V SX SoC Development Board Circuit Diagram (22)
Figure 27. Cyclone V SX SoC Development Board Circuit Diagram (23)
Figure 28. Circuit Diagram of the Cyclone V SX SoC Development Board (24)
Figure 29. Cyclone V SX SoC Development Board Circuit Diagram (25)
Figure 30. Cyclone V SX SoC Development Board Circuit Diagram (26)
Figure 31. Circuit Diagram of the Cyclone V SX SoC Development Board (27)
Figure 32. Circuit Diagram of the Cyclone V SX SoC Development Board (28)
Figure 33. Circuit Diagram of the Cyclone V SX SoC Development Board (29)
Figure 34. Cyclone V SX SoC Development Board Circuit Diagram (30)
Figure 35. Cyclone V SX SoC Development Board Circuit Diagram (31)
Figure 36. Circuit Diagram of the Cyclone V SX SoC Development Board (32)
Figure 37. Circuit Diagram of the Cyclone V SX SoC Development Board (33)
Figure 38. Cyclone V SX SoC Development Board Circuit Diagram (34)
Figure 39. Circuit Diagram of the Cyclone V SX SoC Development Board (35)
Figure 40. Cyclone V SX SoC Development Board Circuit Diagram (36)
Figure 41. Circuit Diagram of the Cyclone V SX SoC Development Board (37)
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