Everyone is a person in the electronics industry. I know a lot about chips and packages. But do you know how a chip is designed? Do you know how the designed chips are produced? After reading this article, you will have a general understanding.
Complex and cumbersome chip design process
The process of chip manufacturing is like using LEGO to build a house. With the wafer as the foundation, and then stacking the stack of chips, the necessary IC chips can be produced (these will be described later). However, without a design, it is useless to have a strong manufacturing capability, so the role of the architect is very important. But who is the architect in the IC design? This article will next introduce the IC design.
In IC manufacturing processes, IC and more by a professional IC design company planning, design, such as MediaTek, Qualcomm, Intel and other well-known manufacturers are designing their own IC chip itself, provide different specifications, performance chips to downstream manufacturers to choose from. Because ICs are designed by each factory, IC design relies heavily on the engineer's technology, and the quality of the engineer affects the value of an enterprise. However, what steps do engineers have when designing an IC chip? The design process can be simply divided into the following.
Design first step, set goals
In IC design, the most important step is specification. This step is like deciding to have several rooms and bathrooms before designing the building. What building regulations are required to follow, and designing after all the functions have been determined, so that no additional time is required for subsequent modifications. IC design also requires similar steps to ensure that the designed chip does not make any mistakes.
The first step in the specification development is to determine the purpose and performance of the IC and to set the direction. Then it is to see which agreements are to be met. Chips like wireless network cards need to comply with IEEE 802.11. Otherwise, the chip will not be compatible with the products on the market, making it impossible to connect with other devices. Finally, the implementation method of this IC is established, the different functions are assigned to different units, and the method of connecting different units is established, so that the specification is completed.
After designing the specifications, the details of the design chip are followed. This step is like taking a preliminary record of the building's plan and drawing out the overall outline to facilitate subsequent drawing. In the IC chip, the circuit is described using a hardware description language (HDL). The commonly used HDL has Verilog, VHDL, etc., and the function of an IC can be easily expressed by the code. The next step is to check the correctness of the program's functionality and continue to modify it until it meets the desired functionality.
â–² Verilog example of the 32 bits adder.
With the computer, things are easy
With the full plan, the next step is to draw a flat design blueprint. In the IC design, logic synthesis is the step of determining the correct HDL code, into the electronic design automation tools (EDA tool), so that the computer converts the HDL code to a logic circuit, a circuit diagram is generated as follows. After that, it is repeatedly determined whether the logic gate design conforms to the specifications and is modified until the function is correct.
â–² The result of the synthesis of the control unit.
Finally, the synthesized code is placed in another EDA tool for Place And Route. After continuous testing, the following circuit diagram will be formed. Different colors such as blue, red, green, and yellow can be seen in the figure, and each different color represents a mask. As for how to use the mask?
â–² Commonly used calculus chip - FFT chip, complete the circuit layout and winding results.
Layered reticle, stacking a chip
First of all, it is known that an IC will produce multiple masks. These masks have separate layers, each with its own task. The following figure shows a simple mask example. Take the most basic component CMOS in the integrated circuit as an example. The full name of CMOS is the complementary metal-oxide-semiconductor, which means that both NMOS and PMOS are used. Combined to form a CMOS. As for what is a metal oxide semiconductor (MOS)? Such components that are widely used in chips are difficult to explain, and it is difficult for general readers to clarify them.
In the figure below, the left side is the circuit diagram formed after the circuit layout and winding. It is known in the front that each color represents a mask. On the right is the way to spread out each mask. The production is started from the bottom layer, following the method mentioned in the previous IC chip manufacturing, layer by layer, and finally the desired chip will be produced.
At this point, there should be a preliminary understanding of IC design. It seems that IC design is a very complex profession as a whole, and thanks to the maturity of computer-aided software, IC design can be accelerated. The IC design factory relies heavily on the wisdom of the engineers. Each step described here has its own specific knowledge. It can be independently developed into a number of professional courses. For example, writing a hardware description language is not simple, only need to be familiar with the programming language. You also need to understand how logic circuits work, how to convert the required algorithms into programs, and how synthetic software converts programs into logic gates.
What is a wafer?
In the semiconductor news, there are always mentions of size-named fabs, such as 8-inch or 12-inch fabs. However, what is the so-called wafer? What part of 8 inch refers to? What is the difficulty in producing large-size wafers? The following is a step-by-step introduction to the most important foundation of semiconductors - what is "wafer"?
Wafer is the basis for manufacturing various computer chips. We can compare the chip manufacturing to the house with Lego bricks, and complete the desired shape (that is, various chips) by stacking one layer after another. However, if there is no good foundation, the house that is covered will come and go, not what you want. In order to make a perfect house, you need a smooth substrate. For chip manufacturing, this substrate is the wafer that will be described next.
(Souse: Flickr/Jonathan Stewart CC BY 2.0)
First of all, let's first think about the fact that when you are a child, you will have a small round protrusion on the surface of the building block. With this structure, we can firmly stack the two blocks without using glue. . Chip fabrication, in a similar manner, holds the subsequently added atoms and substrate together. Therefore, we need to find a substrate with a neat surface to meet the conditions required for subsequent manufacturing.
In solid materials, there is a special crystal structure - monocrystalline. It has the characteristics that atoms are arranged one after another and can form a flat atomic surface. Therefore, using a single crystal to form a wafer can meet the above requirements. However, how to produce such a material has two main steps, namely purification and pulling, respectively, after which the material can be completed.
How to make a single crystal wafer
The purification is divided into two stages. The first step is metallurgical purification. This process is mainly to add carbon to convert the silicon oxide into silicon of 98% or more purity by redox. Most metals are refined, such as metals such as iron or copper, in such a way that metals of sufficient purity are obtained. However, 98% is still insufficient for chip manufacturing and still needs further improvement. Therefore, the Siemens process will be further used for purification, and thus, high-purity polycrystalline silicon required for the semiconductor process will be obtained.
â–² Silicon column manufacturing process (Source: Wikipedia)
Then, it is the step of pulling crystals. First, the high-purity polycrystalline silicon obtained above is melted to form liquid silicon. Thereafter, the single crystal silicon seed is brought into contact with the surface of the liquid, and is slowly pulled up while rotating. As for why a single crystal silicon is needed, it is because the arrangement of silicon atoms is the same as that of people, and it will be necessary to arrange the heads so that later people can arrange them correctly. The silicon species is an important leader, so that later atoms know how to line up. Finally, after the silicon atoms leaving the liquid surface are solidified, the aligned single crystal silicon columns are completed.
â–² Monocrystalline silicon column (Souse: Wikipedia)
However, what does 8 inch and 12 inch represent? He refers to the crystal column we produced, which looks like the part of the pencil holder, and the surface is treated and cut into thin discs. What is the difficulty in manufacturing large-size wafers? As mentioned above, the production process of the crystal column is like making cotton candy, and it is formed while rotating. If you have made marshmallows, you should know that it is quite difficult to make large and solid marshmallows, and the process of pulling crystals is the same. The speed of rotation and the control of temperature will affect the quality of the crystal column. Therefore, the larger the size, the higher the speed and temperature requirements of the crystal pull, so it is more difficult to make a high-quality 12-inch wafer than the 8-inch wafer.
However, a whole silicon column cannot be made into a substrate made of a chip. In order to produce a piece of silicon wafer, the silicon crystal column is then cut into a wafer by a diamond knife, and the wafer can be formed into a wafer by polishing. Fabricate the required silicon wafers. After so many steps, the manufacture of the chip substrate is completed, and the next step is the step of stacking the house, that is, chip manufacturing. As for how to make chips?
Chips stacked on top of each other
After introducing what silicon wafers are, I also know that making IC chips is like building a house with Lego blocks. By layer-by-layer stacking, I create the desired shape. However, there are quite a few steps in building a house. The same is true for IC manufacturing. What are the steps to make an IC? This article will introduce the process of IC chip manufacturing.
Before we start, we must first understand what an IC chip is. IC, the full name of the integrated circuit (Integrated Circuit), by its name, it is known that the circuit is designed to be stacked in a stacked manner. With this method, we can reduce the area required to connect the circuit. The picture below shows the 3D diagram of the IC circuit. It can be seen that its structure is like the beam and column of the house, stacked one by one, which is why the IC manufacturing is compared to the house.
â–² 3D profile of the IC chip. (Source:Wikipedia)
From the 3D cross-section of the IC chip in the above figure, the dark blue part at the bottom is the wafer introduced in the previous article. From this picture, it is more clear that the role of the wafer substrate in the chip is important. As for the red and khaki parts, it is the place to be completed when the IC is made.
First of all, the red part can be compared to the first floor lobby in the tall building. The lobby on the first floor is the gateway to a house. It is here and there. There is usually more functionality under the control of traffic. Therefore, compared with other floors, it will be more complicated to construct and require more steps. In the IC circuit, this hall is the logical gate layer, which is the most important part of the whole IC. By combining various logic gates, a full-featured IC chip is completed.
The yellow part is like a normal floor. Compared with the first floor, there will not be too complicated structures, and each floor will not change much when it is built. The purpose of this layer is to connect the logic gates of the red part together. The reason why so many layers are needed is because there are too many lines to be connected together. In the case where a single layer cannot accommodate all the lines, it is necessary to stack several layers to achieve this goal. Among them, the different layers of the line will be connected up and down to meet the needs of the wiring.
Layered construction
Once you know the construction of the IC, let's talk about how to make it. Imagine if you want to make a fine drawing with a paint spray can, we need to cut off the cover of the graphic and cover it on the paper. Then spray the paint evenly on the paper. After the paint is dry, remove the shutter. By repeating this step, you can complete neat and complex graphics. Manufacturing ICs are stacked in layers in a similar manner by covering them one by one.
When making an IC, you can simply divide it into the above four steps. Although the manufacturing steps are different in actual manufacturing and the materials used are different, similar principles are generally adopted. This process is a little different from painting. IC manufacturing is the first coating and then covering. Paint painting is to cover and paint. The various processes are described below.
Metal Sputtering: Sprinkle the metal material to be used evenly on the wafer to form a film.
Coating photoresist: first place the photoresist on the wafer, pass through the mask (the mask principle is left for the next time), and hit the beam on the unwanted part to destroy the structure of the photoresist. The chemically destroyed material is then washed away.
Etching technology: Silicon wafers that are not protected by photoresist are etched by ion beam.
Photoresist removal: The remaining photoresist is dissolved using the photoresist, so that a process is completed.
In the end, a lot of IC chips will be completed on a whole wafer. Then, if the completed square IC chip is cut, it can be sent to the packaging factory for packaging. What is the packaging factory? I will wait until I will explain later.
â–² Comparison of wafers of various sizes. (Source:Wikipedia)
What is the nanometer process?
Samsung and TSMC have been very hot in the advanced semiconductor manufacturing process. They want to grab the first opportunity in the foundry to win orders, almost 14nm and 16nm, but 14nm and 16nm. What is the meaning of the number and which part is it referring to? What are the benefits and problems that will come in the future after the process is reduced? Below we will make a brief description of the nano-process.
How fine is nanometer?
Before you start, you need to understand what nano is. In mathematics, the nanometer is 0.000000001 meters, but this is a rather poor example. After all, we only see a lot of zeros after the decimal point, but there is no actual feeling. If you compare the thickness of the nail, it may be more obvious.
The actual measurement of the ruler shows that the thickness of the nail is about 0.0001 meters (0.1 mm), which means that the side of a nail is cut into 100,000 lines, each line is about the same as 1 nanometer. This can be slightly imagined how small it is to get 1 nanometer.
Knowing how small the nanometer is, it is also necessary to understand the purpose of shrinking the process. The main purpose of shrinking the transistor is to insert more transistors into the smaller chip, so that the chip will not become more technologically improved. Secondly, it can increase the computing efficiency of the processor; in addition, reducing the volume can also reduce the power consumption; finally, after the chip is reduced in size, it is easier to plug into the mobile device to meet the needs of future thinning.
Let's go back and explore what is the nanometer process. Take 14nm as an example. The process is that in the chip, the line can be as small as 14nm. The figure below shows the phase of the traditional transistor, as an example. The main purpose of shrinking the transistor is to reduce the power consumption. However, which part should be reduced to achieve this goal? The L in the lower left picture is the part we expect to shrink. By reducing the gate length, the current can be routed from the Drain to the Source with a shorter path (you can use Google to search for MOSFETs if you are interested, as explained in more detail).
(Source:)
In addition, the computer is operating with 0 and 1. How do you use a transistor to satisfy this purpose? The practice is to determine if the transistor has current flowing. When the voltage is supplied at the Gate (green square), the current will flow from the Drain to the Source. If no voltage is supplied, the current will not flow, which means 1 and 0. (As for why you should use 0 and 1 for judgment, if you are interested, you can go to Chabrin algebra, we use this method to make a computer)
Size reduction has its physical limitations
However, the process can't be reduced without limit. When we shrink the transistor to about 20 nanometers, we will encounter problems in quantum physics, which will cause leakage of the transistor, which will offset the benefits obtained when the L is reduced. As an improvement, the concept of FinFET (Tri-Gate) is introduced, as shown in the upper right figure. In Intel's previous explanations, it can be known that by introducing this technology, leakage caused by physical phenomena can be reduced.
(Source:)
More importantly, this method can increase the contact area between the Gate side and the lower layer. In the traditional practice (top left), the contact surface has only one plane, but with the FinFET (Tri-Gate) technology, the contact surface will become three-dimensional, and the contact area can be easily increased, so that the same contact can be maintained. The area makes the Source-Drain side smaller, which is quite helpful for downsizing.
Finally, it is why some people say the major plant into the 10-nanometer process will face considerable challenges, mainly due to the size of an atom is about 0.1 nm, in the case of 10 nm, a line less than 100 atoms, It is quite difficult to make, and as long as there is an atomic defect, such as the atom falling out or having impurities during the production process, it will produce an unknown phenomenon that affects the yield of the product.
If you can't imagine this difficulty, you can do a little experiment. On the table, use 100 beads to form a 10×10 square, and cut a piece of paper on the beads, then use a small brush to brush off the adjacent beads, and finally make him form a 10×5 rectangle. In this way, you can know the difficulties faced by the major manufacturers and how difficult it is to achieve this goal.
As Samsung and TSMC will complete mass production of 14nm and 16nm FinFETs in the near future, both of which want to compete for Apple's next-generation iPhone chip foundry, we will see quite exciting commercial competition, and will also get more power saving. Lightweight mobile phones, thanks to the benefits of Moore's Law.
Tell you what is the package
After a long process, from design to manufacturing, I finally got an IC chip. However, a chip is quite small and thin, and if it is not protected, it will be easily scratched and damaged. In addition, because the size of the chip is small, it would not be easy to manually place it on the board if a larger size housing is not used. Therefore, this article will next describe the package.
There are two common packages available today, one is common in electric toys, the black looks like a DIP package, and the other is a BGA package that is common when buying a boxed CPU. As for other methods of packaging, and PGA (Pin Grid Array; Pin Grid Array) or earlier using DIP CPU improved version of a QFP (Plastic Quad Flat Package) and the like. Because there are too many packaging methods, the following will introduce DIP and BGA packages.
Traditional packaging, long-lasting
The first thing to introduce is the Dual Inline Package (DIP). As you can see from the picture below, the IC chip in this package looks like a black enamel under the double-row pins. The encapsulation method is the earliest IC package technology, which has the advantage of low cost and is suitable for small chips that do not need to be connected to too many wires. However, because most of the plastics are used, the heat dissipation effect is poor, which cannot meet the requirements of the current high-speed chips. Therefore, most of the chips that use this package are long-lasting chips, such as the OP741 in the following figure, or an IC chip that is less demanding in operation speed and has smaller chips and fewer holes.
As for the Ball Grid Array (BGA) package, the package size is smaller than that of the DIP, and can be easily placed in a smaller device. In addition, because the pins are below the chip, they can accommodate more metal pins than DIP.
It is quite suitable for chips that require more contacts. However, the use of such a packaging method is costly and the connection method is complicated, so it is mostly used in high unit price products.
â–² The picture on the left shows the chip in the BGA package. The picture on the right shows a BGA schematic using a flip chip package. (Source: Wikipedia on the left)
Mobile devices are on the rise and new technologies are on the stage
However, using these packaging methods consumes a considerable amount of space. Like current mobile devices, wearable devices, etc., a variety of components are required. If each component is packaged separately, the combination will consume a very large space. Therefore, there are currently two methods to meet the requirements of reducing the volume, respectively, SoC ( System On Chip) and SiP (System In Packet).
When the smart phone is just emerging, the term SoC can be found in major financial magazines. But what exactly is SoC? To put it simply, it is to integrate the ICs with different functions into one chip. With this method, not only can the volume be reduced, but also the distance between different ICs can be reduced, and the calculation speed of the chip can be improved. As for the production method, in the IC design stage, different ICs are put together, and then a mask is made through the previously introduced design flow.
However, SoC is not only an advantage, and designing a SoC requires considerable technical cooperation. When IC chips are packaged separately, each package has external protection, and the distance between the IC and the IC is far away, and there is no possibility of mutual interference. However, when all ICs are packaged together, it is the beginning of a nightmare. IC design plants need to change from the original design IC to an IC that understands and integrates various functions, increasing the workload of engineers. In addition, there will be many situations, such as high-frequency signals of communication chips may affect other functions of the IC.
In addition, the SoC needs to be authorized by other vendors' IP (intellectual property) to put other designed components into the SoC. Because the SoC needs to get the design details of the entire IC, a complete mask can be made, which also increases the design cost of the SoC. Maybe someone will question why not design one yourself? Because designing various ICs requires a lot of knowledge related to the IC, only companies like Apple have a budget to dig top engineers from well-known companies to design a brand new IC. R & D is much more cost-effective.
Compromise, SiP appears
As an alternative, SiP jumped onto the stage of integrated chips. Unlike the SoC, it buys ICs from each other and encapsulates them at the last time. This eliminates the need for IP licensing and significantly reduces design costs. In addition, because they are independent ICs, the degree of interference between them is greatly reduced.
â–² Apple Watch uses SiP technology to package the entire computer architecture into a single chip, not only to meet the desired performance but also to reduce the size, so that the watch has more space to put the battery. (Source: Apple's official website)
Products using SiP technology, the most famous non-Apple Watch. Because the internal space of the Watch is too small, it can't use traditional technology, and the design cost of the SoC is too high. SiP is the first choice. With SiP technology, not only can the volume be reduced, but also the distance between ICs can be narrowed, making it a viable compromise. The figure below is a block diagram of the Apple Watch chip, and you can see that quite a few ICs are included.
â–² The internal configuration of the S1 chip in SiP package in Apple Watch. (Source:chipworks)
After the package is completed, it is necessary to enter the test phase. At this stage, it is necessary to confirm whether the packaged IC has normal operation. After correct, it can be shipped to the assembly plant to make the electronic products we have seen. At this point, the semiconductor industry has completed the entire production task.
Antenk Insulation Displacement termination connectors are designed to quickly and effectively terminate Flat Cable in a wide variety of applications. The IDC termination style has migrated and been implemented into a wide range of connector styles because of its reliability and ease of use. Click on the appropriate sub section below depending on connector or application of choice.
An insulation-displacement contact (IDC), also known as insulation-piercing contact (IPC), is an electrical connector designed to be connected to the conductor(s) of an insulated cable by a connection process. The IDC forces a selectively sharpened blade or blades through the insulation, bypassing the need to strip the cable.
IDC Plug / Socket - Card Edge Slot Connector
Card Edge SLOT Connector is the portion of a printed circuit board (PCB) consisting of traces leading to the edge of the board that are intended to plug into a matching socket.
IDC Connectors
The IDC connector is also known as an insulation-displacement contact, or insulation-piercing contact. It is a connector designed to work with ribbon cables, and uses sharp contacts to clamp onto the wire, piercing the insulation and connecting with the wire in a secure and convenient way.
This simple connection principle is ideal for multi-stranded ribbon cables, as it allows the connector to make an assured connection across the multiple wires without having to strip the wires. This cold welding connection may ensure a gas tight connection between the wire and connector.
The Antenk range of IDC connectors includes plug and sockets in configurations to suit your purposes.
IDC Connectors Applications
IDC connections are often used low voltage applications, such as to connect computer drives internally or to connect computer peripheries. They are often cited as preferable due to their having much faster installation speeds than conventional wiring connectors.
IDC connectors also have an advantage in that several IDC connectors can be attached to the same length of ribbon cable, able to handle multiple connections economically, saving time in more complicated installations.
IDC Connectors Features and Benefits
• Fast cold welding connection
• Cost effective
• Versatile
• Quick termination to wire.
Antenk IDC socket connectors are also known as, IDC connectors, IDC socket connectors, IDC socketed connectors, idc connectors, 4x2 idc socket connector, 8 pin idc socket connector, 5x2 idc socket connector, 10 pin idc socket connector, 7x2 idc socket connector, 14 pin idc socket connector, 8x2 idc socket connector, 16 pin idc socket connector, 10x2 idc socket connector, 20 pin idc socket connector, 12x2 idc socket connector, 26 pin idc socket connector, 18x2 idc socket connector, 36 idc socket connector, 20x2 idc socket connector, 40 pin idc socket connector, 25x2 idc socket connector, 50 pin idc socket connector, 30x2 idc socket connector, 60 pin idc socket connector, 32x2 idc socket connector, 64 pin idc socket connector, 2.54mm idc socket connector, 0.10 inch IDC socket connector, IDS socket connector, regular density idc socket connector, PCB idc socket connector, printed circuit board idc socket connector, Ribbon Cable Connectors, ribbon cable idc socket connector, flat ribbon connectors, flat ribbon idc socket connector, flat wire connectors, flat wire idc socket connector, 4x2 IDC socket connector, 8 pin IDC socket connector, 5x2 IDC socket connector, 10 pin IDC socket connector, 7x2 IDC socket connector, 14 pin IDC socket connector, 8x2 IDC socket connector, 16 pin IDC socket connector, 10x2 IDC socket connector, 20 pin IDC socket connector, 12x2 IDC socket connector, 26 pin IDC socket connector, 18x2 IDC socket connector, 36 IDC socket connector, 20x2 IDC socket connector, 40 pin IDC socket connector, 25x2 IDC socket connector, 50 pin IDC socket connector, 30x2 IDC socket connector, 60 pin IDC socket connector, 32x2 IDC socket connector, 64 pin IDC socket connector, 2.54mm IDC socket connector, 0.10 inch IDC socket connector, IDS socket connector, regular density IDC socket connector, PCB IDC socket connector, printed circuit board IDC socket connector, ribbon cable connectors, ribbon cable IDC socket connector, flat ribbon connectors, flat ribbon IDC socket connector, flat wire connectors, flat wire IDC socket connector, IDC socket header, idc socket header, 2.54mm IDC socket header, 0.10 inch IDC socket header, flat ribbon cable, flat ribbon wire, 10 conductor ribbon cable, 16 conductor ribbon wire.
Idc Connector,Idc Socket Connectors,Idc Cable,Idc Socket Fc Connectors,IDC Plug Socket,Card Edge Slot Connector,IDC Box Header,2.54 Micro Match Female IDC connetor,Red DIP Type
ShenZhen Antenk Electronics Co,Ltd , https://www.antenk.com