This article presents the stereo audio interface design based on the KineTIs MK60N512 microcontroller and the 16-bit / 24-bit audio digital-to-analog converter MAX5556. The MK60N512 transmits audio data from the I2S bus to the MAX55 56, and the output audio signal is filtered by an active filter to ensure audio quality while improving its load capacity. MK60N512 internal high-performance programmable enhanced DMA transmits audio data to the I2S module, reducing the burden of the microcontroller core.
introduction
MK60N512 is the highest integrated chip of Freescale ’s KineTIs series of microcontrollers. It is based on the ARM Cortex-M4 core and features low power consumption, high performance, and low cost. It is designed for embedded audio, automotive electronics, and power management. Etc. to provide flexible solutions. The MAX5556 is a low-power, stereo audio digital-to-analog converter (DAC) of the American letter company. It supports the standard I2S bus protocol, with a sampling accuracy of up to 24 bits and a sampling rate of 2 to 50 kHz. Using sigma-delta modulation technology can effectively shape quantization noise and reduce quantization noise.
In the audio processing system, the use of DMA to realize the transmission of audio data in the microcontroller can reduce the participation of the core and reduce the burden on the core. The data transmission channel of the system is shown in Figure 1. The audio signal is temporarily stored in the buffer area and is transmitted by DMA to the sending circuit of the I2S bus module. In order to maintain the continuity of the audio signal, a "ping-pong RAM" design buffer is used. A / B in the figure represents the number of ping-pong RAM.
1 MK60N512 I2S bus and eDMA introduction
1. 1 I2S bus module
The I2S bus module of MK60N512 has three basic operation modes: normal mode, network mode and gated clock mode. For audio applications, the I2S bus module also supports two derivative modes: I2S bus mode and AC97 mode. The structure of the I2S bus module is shown in Figure 2, which is composed of a sending circuit, a receiving circuit, a serial clock and a frame synchronization clock generating circuit. STCK and SRCK are serial transmit and receive clock ports, STFS and SRFS are serial transmit and receive frame synchronization ports, and STXD and SRXD are serial transmit and receive data ports. In synchronous mode, the STCK port is used jointly by the sending and receiving units.
Both the sending circuit and the receiving circuit have two FIFOs with a width of 32 bits and a depth of 15. These FIFOs can be accessed by writing to and reading from the transmit data register TX0 / TX1 and the receive data register RX0 / RX1. The transmission logic transfers the data in the TX FIFO, loads it into the transmission serial shifter TXSR, and then serially transmits from the STXD port; the reception logic transfers the data from the input data frame and puts them into the receiving RXFIFO Entrance. When the number of vacancies in the TX FIFO or the RX FIFO data reaches the set number, an interrupt or DMA transfer will be triggered.
1.2 eDMA
The eDMA of MK60N512 is highly programmable and the data transmission is highly optimized without requiring the intervention of the CPU core. Unlike ordinary DMA, eDMA transmission consists of a major loop (Major Loop) and an auxiliary loop (MinorLoop). The main loop is automatically triggered by the peripherals. After each main loop, the source and destination addresses are automatically shifted according to the values ​​in the TCDn_SOFF and TCDn_DOFF registers without CPU modification. In addition to generating interrupt requests after all transfers are completed, eDMA also supports "half interrupts", that is, interrupt requests are generated when the main loop completes half of the total number of cycles, which is especially suitable for the "ping-pong RAM" design.
2 Introduction to MAX5556
2. 1 pin definition and internal structure
The internal structure of MAX5556 is shown in Figure 3. MCLK is the main clock, LRCLK is the left / right channel selection clock, SCLK is the external serial clock, SDATA is the serial audio input, and OUTL / OUTR are the left / right channel output. After the serial interface module obtains the audio data, it is filtered by a built-in digital interpolator and filter to remove the harmonic noise carried by the baseband audio signal; the audio data is modulated by the sigma-delta modulator and converted by the DAC to output the analog The signal is filtered by an internal analog low-pass filter to attenuate high-frequency quantization noise; the built-in output buffer can drive a load resistance greater than 3 kΩ and a load capacitance up to 100 pF; the final analog audio signal is output from OUTL / OUTR.
2.2 Working mode
The MAX5556 supports external serial clock mode and internal serial clock mode. In a LRCLK cycle, if valid SCLK is detected, it enters the external serial clock mode, and SCLK is used as the sampling clock; if no valid SCLK is detected, it enters the internal serial clock mode, and the sampling clock is generated internally. The frequency of the internal sampling clock is determined according to the ratio of MCLK to LRCLK detected. If the ratio of MCLK to LRCLK is 384, the internal sampling clock frequency is 48 & fmes; fLRCLK; if the ratio of MCLK to LRCLK is 256 or 512, the internal sampling clock The frequency is 32 & TImes; fLRCLK.
2.3 Data format
The MAX5556 supports left-justified 16-bit or 24-bit data format. When it works in external serial clock mode or internal serial clock mode, and the ratio of MCLK to LRCLK is 384 at the same time, the effective data is 24 bits. If the data is less than 24 bits, the low-order bits are filled with zeros; data exceeding 24 bits will be ignored. When working in the internal serial clock mode and the ratio of MCLK to LRCLK is 256 or 512, the effective data is 16 bits. The MAX5556 data format is shown in Figure 4. Each time the second SCLK rising edge after the LRCLK edge changes, the data on SDATA starts to be valid, and the most significant bit (MSB) appears; the least significant bit (LSB) appears after 24 or 16 clock cycles. When LRCLK is 0, data enters the left channel DAC; when LRCLK is 1, data enters the right channel DAC.
3 System hardware circuit design
The MK60N512 transmits audio data to the MAX5556 through the I2S bus for digital-to-analog conversion, and the output analog audio signal is filtered by the filter circuit, while improving the load carrying capacity. The I2S bus module works in the I2S bus master mode. The pins corresponding to the STCK, STFS, and STXD ports of the sending circuit are BCLK, TX_FS, and TXD, respectively. The main clock of the I2S bus module is output through the MCLK pin. The hardware circuit is shown in Figure 5. Since the MK60N512 works at a voltage of 3.3 V, and the MAX5556 works at 5 V, in order to improve the stability of data transmission, the interface uses a pull-up method.
When the LM358 is powered by a single 5 V power supply, the effective output is 1.5 to 3.5 V, and the output of the MAX5556 can reach 0 to 5 V. Therefore, the R1 and R2 are used to attenuate the original signal at the input to prevent the output signal from being clipped. Top distortion.
4 Software design
4.1 "Ping Pong RAM" design
The I2S bus module of MK60N512 supports dual channels in the I2S bus mode, and the audio data is staggered in the FIFO, so the audio data in the buffer also needs to be staggered. The data cache is shown in Figure 6, where L / R represents the audio left / right channel. Each audio data occupies 4 bytes of space, the buffer BUFF_A, BUFF_B is continuous in physical address, they are all 512 bytes in size, a total of 256 audio data are stored. When the DMA reads data from the buffer BUFF_A, the CPU stores the next set of audio signals in the buffer BUFF_B; when the DMA transfers all the data in the BUFF_A, the DMA channel source address is switched to BUFF_B, and at the same time the CPU sends the Store data, so repeatedly.
4. 2 I2S bus module configuration
Configure the I2S bus module to work in the I2S bus master mode. The default data length of one frame is 32 bits, and it is left-aligned mode; use frame synchronization TX_FS as the channel selection clock, and the synchronization frame length is one word. Because the SCLK signal of MAX5556 is provided by MK60N512, the MAX5556 works in the external serial clock mode, and the effective data bit is 24 bits, so the configuration sends the data bit to 24 bits. According to the data format of MAX5556, the data needs to output the TXD data on the falling edge of SCLK, and the early frame synchronization needs to be sent to delay the data by a sampling clock, and the frame frequency needs to be set according to the audio sampling frequency.
Enable the TX FIFO and its DMA request. When the number of vacancies in the FIFO reaches 8, start a DMA main loop. Figure 7 shows the moving process of audio data in TXFIFO. In Fig. 7 (a), the FIFO is full. After the transmit shift logic fetches a data from the FIFO, the FIFO generates a vacancy, as shown in Fig. 7 (b). When the data is sent 8 times, the number of FIFO vacancies reaches 8, the DMA main transmission is triggered, as shown in Figure 7 (c).
The initialization code of the I2S bus is abbreviated-Editor's Note.
4.3 eDMA configuration
When the number of TX FIFO vacancies reaches 8, the DMA main loop is triggered, so the number of data transferred in each main loop is 32 bytes, and the offset of the source address of each main loop is also 32 bytes. 32 main loops. At the end of the 16th main loop, DMA has transferred all the data in BUFF_A, the DMA source address points to BUFF_B, and a "half interrupt" request is generated, and the CPU starts storing the next set of 512-byte audio data in BUFF_A.
When the data transmission in BUFF_B ends, the source address is restored to the BUFF_A start address, and an interrupt request is generated. CPIJ responds to the interrupt and stores the next set of 512-byte audio data in BIJFFB. It can be seen that during the transmission process, the CPU only needs to respond to the interrupt request twice, and then write the audio data to the buffer area. Each time the main loop ends, the source address is offset by 32 bytes. After the complete transfer, the source address is restored to the BUFF_A start address. These operations are completed by the eDMA module itself.
5 Test results
Figure 8 shows the waveforms of TX_FS and TXD. Channel 1 is TX_FS and Channel 2 is TXD. The audio data sent by the left / right channels are all 0x555. The transmission frame frequency of Figure 8 (a) is 48 kHz, and that of Figure 8 (b) is 44.1 kHz. As can be seen from Figure 8, the data length is 24 bits, left-aligned mode, and the data and frame synchronization has a sampling clock delay, in line with the MAX5556 data format and timing.
Conclusion
This article designs a stereo audio interface based on Kinetis MK60N512 and MAX5556. MK60N512 transmits the audio data to MAX5556 through the I2S bus according to the data format and timing of MAX5556. The MAX5556 internal DAC converts the data into analog signals for output, and the audio signals are filtered by the filter circuit. Filtering, while improving the load capacity. Use MK60N512 internal high-performance configurable eDMA to increase the system data transfer rate and reduce the burden on the CPU. Tests show that the system can output stereo audio and the output frequency is adjustable, which can provide a reference for the audio solutions of the Kinetis series of microcontrollers.
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