The high-resolution (HD) security monitoring and processing system at full video frame rate has higher and higher requirements for processing devices, and single-chip DSP processing has been unable to adapt. Multi-chip, multi-core or CPU+DSP methods, although in some cases It can meet the demand, but it still has some problems in terms of PCB cost, system resource occupation and system stability. The new system architecture that uses the flexible nature of FPGAs to load video processing engines is attracting attention.
Cost and performance challenges
Jiang Yungui, senior system architect at Xilinx Asia, said that the market size of the surveillance video intelligent analysis system will reach 800 million US dollars in 2012. For designers and providers of video surveillance network equipment such as cameras and DVRs, single-chip solutions are not commercially or technically feasible due to limitations in processing performance, cost, and power. With the programmable and cost-effective advantages of their Spartan-3A DSP FPGAs, they can meet a variety of monitoring functions such as cameras, virtual obstacles, object lag and demographics, and integrate them into the camera in a single chip.
FPGAs need to be supported by a powerful video processing engine. Eutecus, Inc., of Berkeley, Calif., developed a Cellular Vision Technology (CVT), the next generation of extremely high speed image stream capture and processing technology that integrates independent A large number of parallel processing architectures and algorithms. Stephen D. Hester, president and CEO of Eutecus, said that CVT technology is inspired by the human eye's processing structure, which enables them to provide image processing IP for FPGAs and other devices for the intelligent video surveillance and security markets. “We had a problem developing the Multicore Video Analysis Engine (MVE),†said Hester. “Our first generation is based on TI's DaVinci SoC. But in the second generation, we need more processing power. And system integration. Multiple DSP device solutions are not very cost effective at the cost of the system. We need a port that can easily port the previous generation and provide more features for our second generation MVE. Single chip solution."
Spartan-3A based processing architecture
After some research, E utecus found the Xilinx Spartan-3A DSP3400A. The 126 XtremeDSP DSP48A slices in the device deliver up to 30GMAC of DSP performance, making them ideal for the demanding cost and performance requirements of video analytics applications. MVE is capable of handling HD resolution at video frame rates with power less than 1W. It is an easy-to-configure, compact processing architecture that combines an inherent parallel multi-core processing architecture with embedded complex video analysis algorithms in a configurable building block, simplifying hardware design and programming. MVE can perform multiple event detection and parallel classification algorithms simultaneously.
From one platform to another, portability is an important factor to consider. Xilinx's EDK Embedded Development Kit enables a dual-processor hardware architecture based on the Xilinx MicroBlaze embedded processor, which is similar to TI's DaVinci platform dual-processor hardware architecture. As a result, Eutecus has no concerns about design porting.
"MVE is embedded in the Xilinx Spartan-3A DSP FPGA, enabling complex video analysis functions for smart cameras or other network devices such as single chips in DVRs." Jiang Yungui said, "Using FPGAs can add more video to customers' needs." Analysis capabilities and related event detection examples. A variety of different derivatives can be created using the same hardware platform. Eutecus uses VHDL to design multiple analysis accelerator engines and integrate these dedicated cores into the C-MVA coprocessor. The approach allows engineers to reuse dual MicroBlaze embedded systems to create different FPGA programming files, thus creating a highly scalable solution that can easily accommodate a wide range of video analytics applications."
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